Due to emerging technology and market forces, solid-state drives (SSDs) are steadily replacing previously conventional data storage systems that rely on the rotation of magnetic mediums for reading and writing data (e.g., hard disk drives). Rather than comprising any mechanical or moving parts, solid-state memory comprises integrated circuit assemblies or interconnected flash components to provide non-volatile storage in which stored data can be persistently retained even during a planned or unplanned interruption of power. As a result, a solid-state drive is inherently faster and more robust (i.e., less susceptible to data loss and corruption), as well as consumes less power and is more compact in comparison to disk-based storage. Accordingly, non-volatile memory is a powerful storage solution with respect to many types of computing, consumer electronic, and stand-alone external storage (e.g., USB drives) devices.
With respect to some flash memory types, each individual memory cell comprises a floating gate that is positioned above and isolated from a channel region of a semiconductor substrate, wherein the floating gate is positioned between the source and drain regions. Also, a control gate is provided over and isolated from the floating gate. Accordingly, the threshold voltage (Vth) of the resulting transistor is controlled by and dependent on the amount of charge retained on the floating gate. Specifically, in a switch-like manner, the minimum amount of voltage that must be applied to the control gate before the transistor is activated to permit conduction between its source and drain is determined by the level of charge retained on the floating gate. As a result, bit-value data can be programmed onto and erased from the memory cell by changing the level of charge on a floating gate in order to change the threshold voltage characteristic of the transistor.
As explained in detail below, the number of bits that can be stored in an individual memory cell is dependent upon the number of distinct voltage ranges that may be partitioned within the threshold voltage window of that memory cell. For example, to store one bit of data (referred to as a binary data), the possible threshold voltages of the memory cell are divided into two ranges, wherein the ranges are assigned as logical data “1” and “0” respectively. A memory cell of this type of storage density may be referred to as a “single-level cell” or SLC.
By further partitioning the threshold voltage window of a memory cell into additional distinct voltage ranges, multiple levels of information may be stored. Such a memory cell may be referred to as a “multi-state cell.” For example, to store two bits of data, the threshold voltage window of a cell may be partitioned into four distinct voltage ranges (or states), wherein each range is assigned a bit value equal to, for example, “11,” “10,” “01,” and “00.” Accordingly, after an erase operation, the threshold voltage is negative and may be defined as logic “11.” As such, the positive threshold voltages are used for the states of “10,” “01, “00.” A memory cell of this storage density may be referred to as a “multi-level cell” or MLC. In a further example, in order to store three bits of data, the voltage threshold window of a cell may be partitioned into eight distinct voltage ranges (or states), with each range being assigned a bit value equal to, for example, “111,” “110,” “100,” “010,” “011,” “000,” “001,” and “101.” A memory cell of this storage density may be referred to as a “tri-level” or “triple-level cell” (TLC). The specific relationship between the data programmed into a memory cell and the threshold voltage levels of the memory cell depends upon the data encoding scheme adopted for the memory cells.
Thus, a memory device that comprises multi-state data (by incorporating MLC and/or TLC-type cells) has an increased storage capacity using the same MOSFET structure and wafer size as an SLC-type cell and, as a result, provides a comparative cost per bit savings. However, as a consequence of the increased density and the tightened tolerances between the partitioned voltage ranges of multi-state memory cells, programming occurs at a slower speed relative to a single-state memory cell because the data is programmed to multiple target threshold voltage ranges and requires a higher level of precision during programming. The increased density of a multi-state memory cell decreases the margin of error between state changes and reduces the available voltage range capacity needed to endure the stress on the silicon oxide layer over the successive programming/erase cycles. As a result, in comparison to a single-state memory cell, the durability of a multi-state storage element is significantly lower.
Accordingly, as the industry continues to achieve smaller sized memory cells with increased storage densities in order to store more data, this scaling of size entails certain performance and durability risks. In order to achieve the advantage of higher memory capacity for a fixed die size, smaller memory cells must be packed more closely together. Doing so, however, may result in a greater number of manufacturing, operation, and performance errors, such as shorting (or leakage) between word lines or between word lines and semiconductor substrate. Such errors usually corrupt any data that is stored on pages on the word lines being programmed and neighboring word lines.
Some word line related problems do not manifest themselves at the beginning of the device's life and, as a result, fail after the stress of a number of program and erase cycles. Accordingly, at that point in time, the faulty word line may cause a catastrophic failure of the device as a whole. Therefore, various mechanisms for detecting a word line leakage prior to a failure mode exist in the art and are primarily based on detecting a voltage or current anomaly indicative of a leakage. However, due to the relatively small size of the leakage current and the distortion of such a current attributable to background noise inherent in the device, there is a prevailing need for more precise and efficient leakage detection mechanisms that can operate according to current and voltage levels normally used in the memory operations of the device.